Semiconductor memory devices are binary circuits which store information in arrays of cells arranged in rows and columns. In the fabrication of these devices it is common for an array of memory cells to include one or more defects which prevent the proper performance of the memory circuit. If a type of defect occurs systematically it can often be causally analyzed and designed out. Other defects which are generally not systematic include short circuits between adjacent columns and open circuits within individual columns of memory cells. For analysis purposes the distribution of such defects in a memory device, as well as the distribution of the number of defects among a given production lot, may be considered random so that the yield of good devices in a lot can be modelled according to a Poisson distribution function. Typically, over the period of time that a particular device or family of devices is being produced in a given manufacturing facility the product yield can be improved by eliminating causes, e.g., particulate matter, of the above-mentioned random defects.
Generally, it is desirable to further improve the yield of memory devices by replacing defective segments of an array with redundant circuitry. During testing of the chip, defective columns of memory cells can be identified and replaced. Such redundancy techniques are especially suited for semiconductor memories because these devices comprise large numbers of repeating elements arranged in rows and columns. This array format lends itself to replacement of a defective portion with any of multiple identical redundant circuits.
The redundancy scheme may be implemented by providing a plurality of universal decode circuits for connection to redundant rows or columns. Appropriate fuses are included that can be opened to both activate select portions of the redundant circuitry and program individual circuits to be responsive to the appropriate addresses. For example, in dynamic random access memory devices (DRAM's) address integrity can be maintained by simply programming redundant column or row circuits to respond to defective addresses. Thus the address of each defective column or row is reassigned to a redundant circuit. In video and frame memory circuits the replacement procedure may require greater complexity in order to maintain the sequential nature of memory output. See U.S. Pat. No. 4,598,388 assigned to the assignee of the present invention.
Semiconductor memories of all types are being made with progressively higher bit densities and smaller cell sizes as the density of integrated memory circuits increases. In 1972 4K bit DRAMs were being designed while in 1982 one megabit devices were planned. Device densities of 64 and 256 Megabits may become mass produced during the 1990's. With increased memory capacity there must be improvement in associated performance parameters such as memory access and memory test time. This has necessitated development of more complex memory architectures and implementation of address scrambling formats.
Now, with the development of even denser memories, reduced feature sizes render these devices susceptible to defects caused by particulate matter which previously caused no problems in the fabrication process. Thus with further improvements in density there will be a greater challenge to reduce the number of random-type defects that can be repaired with redundancy schemes.
A problem associated with fabrication of memory devices having progressively greater densities is the increased amount of time required for testing and identifying replacement schemes to remove defects. Since the defects are random, each integrated circuit must be analyzed to identify an individual repair scheme. Total test time for a one megabit memory device is approximately seven seconds. The test time for a wafer can easily exceed 30 minutes. As memory density increases wafer size is expected to increase so that the number of devices formed on a wafer is not expected to decrease dramatically. Thus, as the time required for testing each device increases the time required for testing an entire wafer will increase proportionately For example, with current available technology the process of testing and identifying the repair scheme for a 16 megabit device will easily exceed 100 seconds. Assuming the same technology, the total time for developing replacement schemes for a wafer of 16 megabit devices will clearly exceed 7 hours.
Heretofore, inroads to reduce test and analysis time have come primarily by simultaneously testing several memory devices. For example, this technique has been effected by analyzing four 256K devices at once. Alternately, a one megabit device that is partitioned to provide 256K.times.4 memory can be tested by simultaneously writing test data to each of four 256K blocks of memory cells. A less desirable alternative is to reduce the number of tests performed on a device. This, of course, leads to reliability problems because critical defects which require repair may not be identified without comprehensive testing.
Some improvements have come through program optimization and significant gains in efficiency have also been realized with linear flow programs and by minimizing data manipulation. Nevertheless, further improvements in program efficiency are not seen as a solution to the progressively time consuming task of testing and analyzing memory circuits to provide repair schemes.